In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, and so forth, the processing, storage, and retrieval of information is coordinated with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. A continual demand exists for devices with higher data rates; consequently, circuit designers have begun to focus on ways to increase the frequency of the clock signal. In SDRAMs, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. The delay between a rising edge of the system clock (external to the SDRAM) and the appearance of valid data at the output of the memory circuit is known as the clock access time of the memory. A goal of memory circuit designers is to minimize clock access time as well as to increase clock frequency.
One of the obstacles to reducing clock access time has been clock skew, that is, the delay time between the externally-supplied system clock signal and the signal that is routed to the memory's output circuitry. This skew in the clock signal internal to the integrated circuit is caused by the delays incurred in the signal passing through the clock input buffer and driver and through any associated resistive-capacitive circuit elements. One solution to the problem of clock skew is the use of a synchronous mirror delay as described by T. Saeki, et al. in "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay," IEEE Journal of Solid-State Circuits, vol. 31, No. 11, November 1996, pp. 1656-1665, and also by T. Saeki, et al. in "A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay," 1996 IEEE International Solid-State Circuits Conference, pp. 374-375. The synchronous mirror delay (SMD) is a digital circuit that consists of two delay circuit arrays and one control circuit. The SMD detects the clock cycle from two consecutive pulses, generates a clock-synchronized delay, and eliminates the clock skew, all within two clock cycles.
One problem with the synchronous mirror delay is that with existing technology, the maximum frequency of operation is about 300 MHz. This is in contrast to phase-lock loop (PLL) and delay-lock loop (DLL) designs that have a theoretical maximum frequency closer to 1 GHz. But while PLLs and DLLs offer a higher possible clock frequency, they require several hundreds of clock cycles before skew can be eliminated. To compensate for the slow lock time, designers of systems that incorporate PLLs or DLLs keep these circuits active during the standby mode of the integrated circuit, thereby incurring the penalty of a high standby current. So, the ability to eliminate clock skew quickly and without excessive standby current make SMDs attractive, but the limitations on the maximum frequency of operation of these circuits will become more important as the data rates and operating speeds of future generations of integrated circuits increase.